COSCUP 2025

Open-source EDA shows promising potential in unleashing EDA innovation and lowering the cost of chip design. This paper presents an open-source EDA project, iEDA, aiming for building a basic infrastructure for EDA technology evolution and closing the industrial-academic gap in the EDA area. iEDA now covers digital chip logic synthesis (including logic optimization, technology mapping, automation test pattern generation), the whole flow of physical design (including Floorplan, Placement, CTS, Routing, Timing Optimization etc.), and part of the analysis tools (Static Timing Analysis and Power Analysis). To demonstrate the effectiveness of iEDA, we implement and tape out five chips of different scales (from 700k to 100M gates) on different process nodes (110nm and 28nm) with iEDA. iEDA is publicly available from the project homepage http://ieda.oscc.cc.