2024-08-04, 14:30–15:00 (Asia/Taipei), TR611
There is still very few free/open-source/multiple issue/in-order/softcore CPU in the wild. At the same time, VexRiscv accumulated quite some technical debt and limitations. So it was time to fill those gaps !
VexiiRiscv aim at :
- Providing a free/open-source CPU which can scale from simple micro controller, up to linux ready multi-core / multi-issue cluster (Cortex A53/A55 like)
- Covering both 32 bits and 64 bits RISC-V + IMAFDC + B
- Being very modular and extendable
- Being Debian capable
- Being FPGA friendly
This talk should normaly run on the hardware itself (FPGA + VexiiRiscv + Debian), minus maybe, some kernel panics ^.^
Working in open-source hardware since 2015. Here is a few projects :
- Hardware description library : SpinalHDL
- RISC-V CPU : VexRiscv, VexiiRiscv, NaxRiscv
I'm working as an independent, living from the project listed above.