COSCUP 2023

Successful open-source software inspires many technologies. Young engineers or students will learn many things from existing REAL designs.
Unlike open-source software, VLSI design tasks are usually covered by NDA from fabrication companies and EDA tool vendors. It will prevent students to learn from existing designs.
We wanted to change the situation. For educational purposes, we are trying to establish open VLSI fabrication methodologies. The methods are based on scalable cell libraries and scalable layout rules.
With our method, we have made VLSI chips with several fabrication processes which will not require NDA from the designing students. These chips use legacy technologies such as 2-micron, 1.2-micron, 600nm, 350nm, and 180nm. But we believe that adaptations to other finer technologies will not be difficult and the method will contribute to the students and startups to learn faster from existing designs and challenge their own new ideas on VLSI.

Starting in 1990, Sorbonne Université-CNRS/LIP6 developped Alliance, a
complete VLSI CAD toolchain released under GPL. In this spirit, we
are assembling an upgraded design flow for ASICs based on FOSS tools
like GHDL & Yosys for logical synthesis and Coriolis for physical
design. We will present the flow with a focus on the Cotiolis part and
some of the designs we made. This should be an important milestone
toward the creation of an open hardware community.